Validation of Speculative and Out - of - order ExecutionMicroarchitecture 1

We validate speculative and out-of-order execution microarchitecture using an ATPG-like methodology. The validation methodology uses FSM models derived from microarchitecture speciications. Complete transition tours are generated from the FSM models to obtain a high-level test sequence. Small assembly sequences associated with each FSM transition are used to translate FSM testing sequences into simulatable test programs. The methodology is demonstrated on the speculative and out-of-order execution mechanisms of the PowerPC 604. The eeectiveness of our sequences is compared with some real programs by measuring transition coverage. Simulation results show that all targeted FSM transitions are covered by our sequences. Real programs can achieve the same coverage for some portions of the targeted functionality but use 1000X more instructions.